DOCUMENT AMIGA 1200 ***************************************************************************************************************************** U2 Alice Pinouts@} Type: 8374 Position: U2 Desc: AA Agnus | 1 b DRD29 DRAM Data Bus Bit 29 | 43 o DRA0 DRAM Addr. Bus Bit 0 2 b DRD28 DRAM Data Bus Bit 28 | 44 o DRA1 DRAM Addr. Bus Bit 1 3 b DRD27 DRAM Data Bus Bit 27 | 45 o DRA2 DRAM Addr. Bus Bit 2 4 b DRD26 DRAM Data Bus Bit 26 | 46 o DRA3 DRAM Addr. Bus Bit 3 5 b DRD25 DRAM Data Bus Bit 25 | 47 o DRA4 DRAM Addr. Bus Bit 4 6 b DRD24 DRAM Data Bus Bit 24 | 48 o DRA5 DRAM Addr. Bus Bit 5 7 b DRD23 DRAM Data Bus Bit 23 | 49 o DRA6 DRAM Addr. Bus Bit 6 8 b DRD22 DRAM Data Bus Bit 22 | 50 o DRA7 DRAM Addr. Bus Bit 7 9 b DRD21 DRAM Data Bus Bit 21 | 51 o DRA8 DRAM Addr. Bus Bit 8 10 b DRD20 DRAM Data Bus Bit 20 | 52 VCC +5v 11 b DRD19 DRAM Data Bus Bit 19 | 53 12 b DRD18 DRAM Data Bus Bit 18 | 54 o _CAS Column Addr. Strobe 13 b DRD17 DRAM Data Bus Bit 17 | 55 b A20 Address Bus Bit 20 14 b DRD16 DRAM Data Bus Bit 16 | 56 o DRA9 DRAM Addr. Bus Bit 9 15 _RESET Reset (tied to GND) | 57 o _RAS Row Address Strobe 16 | 58 GND Ground 17 o _INT3 Interrupt Request 3 | 59 b A19 Address Bus Bit 19 18 i DMAL DMA Request Line | 60 b A1 Address Bus Bit 1 19 | 61 b A2 Address Bus Bit 2 20 | 62 b A3 Address Bus Bit 3 21 o _DWE Disk Write Enable | 63 b A4 Address Bus Bit 4 22 b R_W Read/Write | 64 b A5 Address Bus Bit 5 23 | 65 b A6 Address Bus Bit 6 24 | 66 b A7 Address Bus Bit 7 25 | 67 b A8 Address Bus Bit 8 26 o RGA8 Register Addr. Bus 8 | 68 b A9 Address Bus Bit 9 27 o RGA7 Register Addr. Bus 7 | 69 b A10 Address Bus Bit 10 28 o RGA6 Register Addr. Bus 6 | 70 b A11 Address Bus Bit 11 29 o RGA5 Register Addr. Bus 5 | 71 b A12 Address Bus Bit 12 30 o RGA4 Register Addr. Bus 4 | 72 b A13 Address Bus Bit 13 31 o RGA3 Register Addr. Bus 3 | 73 b A14 Address Bus Bit 14 32 o RGA2 Register Addr. Bus 2 | 74 b A15 Address Bus Bit 15 33 o RGA1 Register Addr. Bus 1 | 75 b A16 Address Bus Bit 16 34 i SCLK | 76 b A17 Address Bus Bit 17 35 i 14MHZ 14MHz Signal | 77 b A18 Address Bus Bit 18 36 | 78 i _FIRE1 Joystick 1 Fire 37 _CDAC 7MHZ Quadrature Clock * | 79 b _VSYNC Vertical Sync 38 7MHZ 7MHz Signal * | 80 o _CSYNC Composite Sync 39 o CCKQ Colour Clock Quadrat. | 81 b _HSYNC Horizontal Sync 40 o CCK Colour Clock | 82 GND Ground 41 i _NTSC NTSC/PAL Display | 83 b DRD31 DRAM Data Bus Bit 31 42 GND Ground | 84 b DRD30 DRAM Data Bus Bit 30 | * 7MHz means 7.15909MHz on NTSC systems and 7.09378MHz on PAL systems Type: 4145F023A Position: U5 Desc: AA Gayle Function: Oooh, lots of control stuff | 1 o PE12 | 43 b A14 Address Bus Bit 14 2 o PE5 | 44 b A15 Address Bus Bit 15 3 GND Ground | 45 GND 4 o NOISE | 46 b A16 Address Bus Bit 16 5 o _CC_RESET PCMCIA Reset | 47 b A17 Address Bus Bit 17 6 o _CC_ENA PCMCIA Enable | 48 b A18 Address Bus Bit 18 7 o _REG | 49 b A19 Address Bus Bit 19 8 o _WE DRAM Write Enable | 50 b A20 Address Bus Bit 20 9 o _OE | 51 b A21 Address Bus Bit 21 10 o E Peripheral Enable Clk | 52 b A22 Address Bus Bit 22 11 o _FLASH | 53 b A23 Address Bus Bit 23 12 i _IDE_IRQ | 54 b D15 Data Bus Bit 15 13 i _IDE_CS1 | 55 b D14 Data Bus Bit 14 14 i _IDE_CS2 | 56 b D13 Data Bus Bit 13 15 o _SPARE_CS | 57 b D12 Data Bus Bit 12 16 o _NET_CS | 58 b D11 Data Bus Bit 11 17 o _RTC_CS | 59 b D10 Data Bus Bit 10 18 o _IOWR I/O Write | 60 b D9 Data Bus Bit 9 19 o _IORD I/O Read | 61 b D8 Data Bus Bit 8 20 VCC +5v | 62 i _BEER Bus Error 21 | 63 i _KB_RESET Keyboard Reset 22 o CPUCLK CPU Clock | 64 23 o CCK Colour Clock | 65 GND Ground 24 GND | 66 25 i XRDY External Data Ready | 67 o _MTR0 DF0: Motor On 26 i _OVR Override Sys. Decoding | 68 27 o _CC_AO | 69 b FC1 Function Code Bit 1 28 _DEB | 70 b FC0 Function Code Bit 0 29 _DBR | 71 i _MTR Floppy Motor On 30 _BLS | 72 i _SEL0 Floppy Select 0 31 _REGEN Chip Register Enable | 73 o _ODD_CIA {CIA Timing 32 _RAMEN RAM Enable | 74 o _EVEN_CIA {Signals 33 b _AS Address Strobe | 75 i _CC_CD1 34 b _DS Data Strobe | 76 i _CC_CD2 35 i _DSACK1 Data Send Acknowledge1 | 77 i _CC_BVD1 36 b R_W Processor Read/Write | 78 i _CC_BVD2 37 i _DSACK0 Data Send Acknowledge0 | 79 i _CC_WP 38 | 80 i _CC_BUSY_IREQ 39 b _HLT Processor Halt | 81 i _WAIT Processor Wait 40 b _RST Processor Reset | 82 VCC +5v 41 b A12 Address Bus Bit 12 | 83 o _INT6 {Interrupt 42 b A13 Address Bus Bit 13 | 84 o _INT2 {Requests | Lisa Pinouts@} Type: 4203 Position: U4 Desc: AA Denise Function: Video is just about it, really. | 1 GND Ground | 43 o CLOCK 2 b DRD6 DRAM Data Bus Bit 6 | 44 o G4 Green Bit 4 3 b DRD5 DRAM Data Bus Bit 5 | 45 o G5 Green Bit 5 4 b DRD4 DRAM Data Bus Bit 4 | 46 o G6 Green Bit 6 5 b DRD3 DRAM Data Bus Bit 3 | 47 o G7 Green Bit 7 6 b DRD2 DRAM Data Bus Bit 2 | 48 o R0 Red Bit 0 7 b DRD1 DRAM Data Bus Bit 1 | 49 o R1 Red Bit 1 8 b DRD0 DRAM Data Bus Bit 0 | 50 o R2 Red Bit 2 9 i _BCAS_XX | 51 o R3 Red Bit 3 10 i CCK Colour Clock | 52 o R4 Red Bit 4 11 | 53 GND Ground 12 i RGA8 Register Addr. Bus Bit 8| 54 o R5 Red Bit 5 13 i RGA7 Register Addr. Bus Bit 7| 55 o R6 Red Bit 6 14 i RGA6 Register Addr. Bus Bit 6| 56 VCC +5v 15 i RGA5 Register Addr. Bus Bit 5| 57 o R7 Red Bit 7 16 i RGA4 Register Addr. Bus Bit 4| 58 o _BURST NC 17 i RGA3 Register Addr. Bus Bit 3| 59 b DRD31 DRAM Data Bus Bit 31 18 i RGA2 Register Addr. Bus Bit 2| 60 b DRD30 DRAM Data Bus Bit 30 19 i RGA1 Register Addr. Bus Bit 1| 61 b DRD29 DRAM Data Bus Bit 29 20 i MDAT | 62 b DRD28 DRAM Data Bus Bit 28 21 o _MLD | 63 b DRD27 DRAM Data Bus Bit 27 22 o SCLK | 64 b DRD26 DRAM Data Bus Bit 26 23 o 14MHZ 14MHz Clock Signal | 65 b DRD25 DRAM Data Bus Bit 25 24 | 66 b DRD24 DRAM Data Bus Bit 24 25 i 28MHZ 28MHz Clock Signal | 67 b DRD23 DRAM Data Bus Bit 23 26 | 68 b DRD22 DRAM Data Bus Bit 22 27 | 69 b DRD21 DRAM Data Bus Bit 21 28 | 70 b DRD20 DRAM Data Bus Bit 20 29 o B0 Blue Bit 0 | 71 b DRD19 DRAM Data Bus Bit 19 30 VCC +5v | 72 b DRD18 DRAM Data Bus Bit 18 31 o B1 Blue Bit 1 | 73 b DRD17 DRAM Data Bus Bit 17 32 o B2 Blue Bit 2 | 74 b DRD16 DRAM Data Bus Bit 16 33 GND Ground | 75 b DRD15 DRAM Data Bus Bit 15 34 o B3 Blue Bit 3 | 76 b DRD14 DRAM Data Bus Bit 14 35 o B4 Blue Bit 4 | 77 b DRD13 DRAM Data Bus Bit 13 36 o B5 Blue Bit 5 | 78 b DRD12 DRAM Data Bus Bit 12 37 o B6 Blue Bit 6 | 79 b DRD11 DRAM Data Bus Bit 11 38 o B7 Blue Bit 7 | 80 b DRD10 DRAM Data Bus Bit 10 39 o G0 Green Bit 0 | 81 b DRD9 DRAM Data Bus Bit 9 40 o G1 Green Bit 1 | 82 b DRD8 DRAM Data Bus Bit 8 41 o G2 Green Bit 2 | 83 VCC +5v 42 o G3 Green Bit 3 | 84 b DRD7 DRAM Data Bus Bit 7 | Video Port Pinout@} ,----------------------------------------, Type: Male 23-way D \\ 1 2 3 4 5 6 7 8 9 10 11 12 / Used: Monitors \\ 13 14 15 16 17 18 19 20 21 22 23 / Graffitti "Video Card" '-----------------------------------' 1: _XCLK External Clock 13: GNDRTN Return for /XCLKEN 2: _XCLKEN External Clock Enable* 14: _PIXELSW Genlock Overlay* 3: RED Analog Red** 15: _C1 Clock Out* 4: GREEN Analog Green** 16: GND Video Ground 5: BLUE Analog Blue** 17: GND Video Ground 6: DI Digital Intensity* 18: GND Video Ground 7: DB Digital Blue* 19: GND Video Ground 8: DG Digital Green* 20: GND Video Ground 9: DR Digital Red* 21: -12V -12v DC (10mA) 10: _CSYNC Composite Sync* 22: +12V +12v DC (100mA) 11: _HSYNC Horizontal Sync* 23: +5V +5v DC (100mA) 12: _VSYNC Vertical Sync* Pin 13 can be considered Digital Ground Signals marked * are 47 Ohm Signals marked ** are 75 Ohm As motherboards go, the one found inside the A1200 is pretty boring. First thing you'll notice is that there are no jumpers. There is no SCSI or fast memory as standard, unlike its bigger cousins, so it doesn't need them. Second thing you'll notice is that, like the A600, it contains 90% surface-mount technology - only the ROM's are socketed. While this is bad news for hackers due to it's complexity, or for people who like blowing chips (even the CIA's are SMD), it offered greater reliability over the socketed motherboards of old. Layout Power Video C Parallel Audio Serial Floppy Joystick ,---------------------------------------------------------------------------, | 6_________ 16 | | '---------' ______ :::::::::: ,-| | ::2 11| | | | | :: | | 14 '-| | :: ______ | | :::: 17 | | :: |3 | ,------, | | 15 | |-, :: | | |7 | |______| .-----------------------' |1| '------' |______| ::::::: 13=| | | ,------. .______________. 12 =| | | |4 | 8|______________| =| | | |______| .______________. =| |-' ______ 9|______________| =| | |5 | _____ =| | 18 18 | | ..18.. 10| | =| | ...... '------' |_____| =| '---------------------------------------------------' main board 1: PCMCIA Port 10: 68EC020 CPU (U1) 2: IDE Connector (CN16) 11: 4x 512k 70ns RAM 3: Lisa (U4) 12: Clock Header 4: Gayle (U5) 13: 150-way Expansion Slot 5: Alice (U2) 14: Floppy Drive Power 6: Keyboard Ribbon Connector 15: Pwr/FD/HD LED Output 7: Budgie 16: Floppy Drive Data 8: ROM 1 (U6B) 17: Mouse Port Connector 9: ROM 0 (U6A) 18: Test Points The mouse port is usually a seperate part. On some machines it is a square bit of circuit board, which plugs into a right-angle connector, while on others it is just a port on the end of a IDC cable, which plugs into a DIL header on the motherboard. Both connections are in the position indicated above. On very early machines, it's part of an extended motherboard and so no additional piece is used. I guess Commodore redesigned it because there was a lot of wasted PCB there. Revisions Two main revisions of the A1200 motherboard were produced, Rev 1D and Rev 2B. They only differed in the type of RAM chips used for the Chip RAM. There was quite a shortage of RAM chips, and so measures were taken to ensure that production could keep going whatever chips were available. One took 8bit RAM, while the other took 16 bit and production was switched depending on what was available. (Thanks to Dr. Peter Kittel for that)
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